Recently, a semiconductor apparatus has been accommodated in a multi-terminal package such as a BGA (Ball Grid Array) or a CSP (Chip Size Package). In such a semiconductor apparatus (generally speaking, also referred to as a semiconductor package), a semiconductor device is implemented on an interposer substrate (generally speaking, also referred to as an interposer), and the interposer substrate is implemented on a board such as a mother board.
FIG. 19 is a plan view of an interposer substrate 104P according to prior art, on which a semiconductor device 102 is implemented. Referring to FIG. 19, the semiconductor device 102 includes a plurality of terminals 121. A plurality of connection terminals (generally speaking, also referred to as input and output terminals or electrode pads) 141 are formed on a surface of the interposer substrate 104P. The terminals 121 of the semiconductor device 102 are electrically connected to the connection terminals 141 of the interposer substrate 104P, respectively, using wires 151. In FIG. 19, the terminals 121 are connected to the connection terminals 141 by wire bonding, however, the terminals 121 are often connected to the connection terminals 141, respectively, by bumps.
Further, on the surface of the interposer substrate 104P, connection wiring conductors 142 are formed. One end of the connection wiring conductor 142 is connected to one connection terminal 141, and another end of the connection wiring conductors 142 is connected to one end of one of via conductors 144 formed in the interposer substrate 104P. Another end of the via conductor 144 is electrically connected to a wiring formed on a back surface or inside of the interposer substrate 104P. Further, each of the wirings formed on the back surface or inside of the interposer substrate 104P is electrically connected to one of electrode pads formed on a mother board via a solder ball or the like.
In this case, generally speaking, the connection terminals 141 on the interposer substrate 104P is subjected to a noble metal plating (for example, a gold plating) treatment using electroplating. During this noble metal plating treatment, an electric current is applied to each of the connection terminals 141 via wirings formed on the interposer substrate 104P from an outer edge part of the interposer substrate 104P. After the application of the current, in each of the wirings, a part of the wiring used for the application of the current is used as the connection wiring conductor 142, which connects the connection terminal 141 to the via conductor 144. The remaining part of the wiring remains as the plating stub conductor 145 (generally speaking, also referred to as a plating line) extending from the via conductor 144 to the outer edge part of the interposer substrate 104P. Namely, one end of the plating stub conductors 145 is connected to one via conductor 144, and another end of the plating stub conductor 145 is an open end and forms an open end portion on the outer edge part of the interposer substrate 104P.
It has been known that the plating stub conductors 145 of the interposer substrate 104P have bad influence upon waveforms of transmitting signals transmitted via the connection wiring conductors 142. For example, Patent Document 1 points out such a problem that a waveform distortion occurs to an inputted signal inputted to a connection wiring conductor connected to a plating stub conductor, because of interference between the inputted signal and a reflected signal reflected by the open end of the plating stub conductor. In order to solve this problem, Patent Document 1 proposes eliminating remaining plating stub conductors. In addition, in order to solve a problem similar to above, Patent Document 2 proposes connecting the plating stub conductors to terminal resistors.